The difficulty in the fabrication of small geometry high-performance metal oxide semiconductor field-effect transistors (MOSFETS) is the following quandary: if the source/drain junctions are doped to a level high enough to give reasonably low series resistance, the magnitude of the electric field in the channel adjacent the drain during the on state will be so high that hot carriers and impact ionization effects will become a nuisance and result in lifetime degradation.
As the MOSFET channel becomes shorter, the electric field along the channel becomes stronger (for a given power supply voltage). That is, the potential distribution becomes two dimensional, and the effect of the electric field along the channel can no longer be ignored while considering the effects of the electric field normal to the channel. In particular, where the electric field along the channel is high, as is likely to be in short channel MOS devices, impact ionization is likely to occur near the drain. The resulting substrate current greatly increases the likelihood of device latchup in CMOS technologies. In addition, hot carriers are also likely to be generated by the strong electric field magnitude near the drain, and some of these carriers may be injected into the gate oxide, leading to threshold voltage shift and transconductance degradation.
One approach to minimize the degradation is to reduce the electric field at the drain region to prevent the carriers from achieving sufficient energy to be injected into the gate oxide. This is achieved by grading the junction of the drain by doing two implants into the source/drain region. One of the implants is designed to create a lighter doped region beyond the normal N+ drain region. This can be done by offsetting the heavier implant with a sidewall spacer forming the drain structure, sometimes called a lightly doped drain (LDD). Another approach is simply to do two implants of phosphorus and arsenic in the same region to form a structure which is sometimes called a double doped (or double diffused) drain (DDD). The electric field in the drain region is reduced for both these structures due to the graded drain doping.
With conventional LDD structures, however, it is difficult to independently control the two portions of the LDD regions, namely the overlapped portion which is below the transistor gate and the non-overlapped portion which is not below the transistor gate. Prior art methods which utilize diffusion processes to form the LDD regions cannot control the lateral movement under the gate as well as the depth of the junction independently.
Another method to form an LDD region entails performing an ion implantation under the gate after the gate has been formed. In this method, the ions are implanted at an angle so that impurities may be driven beneath the gate. This process, however, is difficult to control since once again the impurities will be driven downwards as well as laterally under the gate. In other words, there is limited control over the length of the overlapped LDD region and lack of independent control over the LDD region junction depth and lateral overlapped LDD length.
Accordingly, improvements which overcome any or all of the problems are presently desirable.